Gap and trenches such as shallow trench isolation structures (STIs) are commonly employed to electrically isolate elements on semiconductor devices. An STI may include a trench or gap formed in an isolation region of a semiconductor substrate that is filled with a dielectric material to hinder the electrical coupling of nearby device structures (e.g., transistors, diodes, etc.). As the device density on integrated circuits continues to increase, the size and distance between device structures is decreasing. However, the vertical heights of the STIs normally do not decrease as fast as their horizontal widths, resulting in gaps and trenches with larger ratios of height to width (i.e., higher aspect ratios).
While the ability to make device structures with increasing aspect ratios allows more of the structures (e.g., transistors, capacitors, diodes, etc.) to be packed onto the same surface area of a semiconductor chip substrate, it has also created fabrication problems. One of these problems is the difficulty of completely filling the gaps and trenches in these structures without creating a void or seam during the filling process. Filling gaps and trenches with dielectric materials like silicon oxide is necessary to electrically isolate nearby device structures from each other to minimize electrical noise and current leakage. As aspect ratios increase, it becomes more difficult to fill deep narrow trenches without creating a void or seam in the dielectric material that fills the trench.
Voids and seams in a dielectric layer cause problems both during semiconductor device fabrication and in the finished devices. The voids and seams are formed randomly in the dielectric material and have unpredictable sizes, shapes, locations and densities. This results in unpredictable and inconsistent post-deposition processing of the layer, such as uneven etching, polishing, annealing, etc. The voids and seams in the finished devices also create variations in the dielectric qualities of gaps and trenches in device structures. This can result in erratic and inferior device performance due to electrical crosstalk, charge leakage, and in some instances, shorting within the device, among other problems.
Techniques have been developed to minimize the formation of voids and seams during deposition of dielectric materials on high aspect ratio structures. These include slowing the deposition rate of the dielectric material so it stays more conformal to the sidewalls and bottom of the trench. A more conformal deposition can reduce material build up at the top of the trench and the chance of dielectric material prematurely sealing off the top of the trench to form a void (a problem sometimes referred to as “breadloafing”). Unfortunately however, slowing the deposition rate also means increasing the deposition time, which reduces processing efficiency and production rates.
Another technique to control void formation is to increase the flowability of the deposited dielectric material. A material with more flowability can more quickly fill a void or seam and prevent it from becoming a permanent defect in the fill volume. For example, highly flowable spin-on-glass (SOG) precursors like PSZ films, SAM 24, BTBAS, etc., were conventionally employed for filling trenches with good conformality. However, increasing the flowability of an silicon oxide dielectric material by such conventional SOG films often results in an as-deposited films with low film density caused by residual carbon and silanol groups. One approach to increased film densification is to use high-temperature annealing when curing the SOG film into a silicon oxide film. However, the high-temperature annealing used to remove residual carbon and OH groups may also cause a considerable degree of volumetric shrinkage of film. In narrow trenches for STI applications, the as-deposited films are constrained and unstable to shrink, resulting low density films with porous or void containing structures.
Thus, there remains a need for improved processes for increasing the density of the dielectric films in the trenches, gaps, and other device structures with high aspect ratios to achieve void-free gapfills. There also remains a need for dielectric deposition processes that can deposit dielectric materials at high rates and good flowability characteristics without adversely affecting the quality of the finished gapfill. These and other aspects of dielectric film deposition are addressed by the present invention.